1. Field of the Invention
This invention relates to a memory system and a control method thereof, and, for example, a memory system having a NAND flash memory.
2. Description of the Related Art
Recently, nonvolatile semiconductor memories are used in various portions such as large-scale computers, personal computers, home electrical appliances, portable telephones and the like. Particularly, NAND flash memories are nonvolatile semiconductor memories that are electrically rewritable and can be formed with large capacity and high integration density. Further, recently, it is considered to use the NAND flash memory instead of a hard disc drive (HDD).
The NAND flash memory is a semiconductor memory that requires an erase process before a write process is performed. The service life thereof depends on the number of rewrite operations. The data write/erase operation in the NAND flash memory is to inject/discharge electrons with respect to the floating gate by applying high voltage between the substrate and the control gate. If the above operation is performed by a large number of times, the gate oxide film lying around the floating gate is degraded and electrons injected into the floating gate are extracted to destroy data. That is, when the number of rewrite operations is increased, a period in which data is kept retained after data was written becomes short (the retention characteristic is degraded).
Further, data recorded by use of personal computers and the like has both of time locality and regional locality (Document 1: David A. Patterson and John L. Hennessy, “Computer Organization and Design: The hardware/Software Interface”, Morgan Kaufmann Pub, 2004, Aug. 31). Therefore, if data items are sequentially recorded as they are in addresses specified from the exterior when data is recorded, the rewrite processes, that is, erase processes are concentrated in a specified region in a short period and thus the number of erase processes becomes largely unbalanced.
It is known that the service life of the NAND flash memory also depends on the interval between the erase processes and the retention characteristic becomes better and the service life becomes longer as the interval becomes longer (Document 2: Neal Mielke et al., “Flash EEPROM Threshold Instabilities due to Charge Trapping During Program/Erase Cycling”, IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 4, NO. 3, SEPTEMBER 2004, PP. 335-344). This also indicates that the retention characteristic becomes degrading and the service life becomes shorter as the erase interval becomes shorter.
Further, it is known that the retention characteristic is recovered even when the write operations are performed at short intervals unless an erase process is performed for a corresponding long period (Document 3: Neal Mielke et al., “Recovery Effects in the Distributed Cycling of Flash Memories”, 44th Annual International Reliability Physics Symposium, San Jose, 2006, PP. 29-35).